/////////////////////////////////////////////////////////////////////
////                                                             ////
////  Author: Eyal Hochberg                                      ////
////          eyal@provartec.com                                 ////
////                                                             ////
////  Downloaded from: http://www.opencores.org                  ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2010 Provartec LTD                            ////
//// www.provartec.com                                           ////
//// info@provartec.com                                          ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
//// This source file is free software; you can redistribute it  ////
//// and/or modify it under the terms of the GNU Lesser General  ////
//// Public License as published by the Free Software Foundation.////
////                                                             ////
//// This source is distributed in the hope that it will be      ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
//// PURPOSE.  See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html              ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
//---------------------------------------------------------
//-- File generated by RobustVerilog parser
//-- Version: 1.0
//-- Invoked Fri Mar 25 23:34:54 2011
//--
//-- Source file: dma_ch_periph_mux.v
//---------------------------------------------------------



  
module dma_axi32_core0_ch_periph_mux(clk,reset,clken,periph_req,periph_clr,periph_ready,periph_num,clr_valid,clr);

   input                    clk;
   input             reset;
   input             clken;
   
   input [31:1]         periph_req;
   output [31:1]         periph_clr;
   output             periph_ready;
   input [4:0]              periph_num;
   input             clr_valid;
   input             clr;

   
   reg [31:1]             periph_clr;
   wire [31:0]             periph_req_full;
   wire             periph_ready_pre;
   

   always @(/*AUTOSENSE*/clken or clr or clr_valid or periph_num)
     begin
    periph_clr = {31{1'b0}};

    periph_clr[periph_num] = clr & clr_valid & clken;
     end


   assign periph_req_full  = {periph_req, 1'b1}; //bit 0 is memory
   assign periph_ready_pre = periph_req_full[periph_num];

   prgen_delay #(1) delay_ready  (.clk(clk), .reset(reset), .din(periph_ready_pre), .dout(periph_ready));

   
endmodule






